EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 13

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.1.4 Exceptions and interrupts
2.1.5 Data types
2.1.6 The Cortex Microcontroller Software Interface Standard
2011-02-04 - d0002_Rev1.00
Table 2.10. CONTROL register bit assignments
Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer
bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms update
the CONTROL register.
In an OS environment, it is recommended that threads running in Thread mode use the process stack
and the kernel and exception handlers use the main stack.
By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP,
use the MSR instruction to set the Active stack pointer bit to 1, see Section 3.10.7 (p. 83) .
Note
The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested
Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the
normal flow of software control. The processor uses handler mode to handle all exceptions except for
reset. See Section 2.3.7.1 (p. 27) and Section 2.3.7.2 (p. 27) for more information.
The NVIC registers control interrupt handling. See Section 4.2 (p. 88) for more information.
The processor:
• supports the following data types:
• supports 64-bit data transfer instructions.
• manages all data memory accesses as little-endian. See Section 2.2.1 (p. 15) for more information.
For a Cortex-M3 microcontroller system, the Cortex Microcontroller Software Interface Standard
(CMSIS) defines:
• a common way to:
Bits
[31:2]
[1]
[0]
• 32-bit words
• 16-bit halfwords
• 8-bit bytes
Name
-
Active stack pointer
Thread mode privilege level
When changing the stack pointer, software must use an ISB instruction immediately after
the MSR instruction. This ensures that instructions after the ISB execute using the new stack
pointer. See Section 3.10.5 (p. 82)
Function
Reserved
Defines the current stack:
0 = MSP is the current stack pointer
1 = PSP is the current stack pointer.
In Handler mode this bit reads as zero and ignores writes.
Defines the Thread mode privilege level:
0 = privileged1 = unprivileged.
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