EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 64

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.5.6.5 Example
3.5.7 MOVT
3.5.7.1 Syntax
3.5.7.2 Operation
3.5.7.3 Restrictions
3.5.7.4 Condition flags
3.5.7.5 Examples
3.5.8 REV, REV16, REVSH, and RBIT
3.5.8.1 Syntax
2011-02-04 - d0002_Rev1.00
• update the N and Z flags according to the result
• can update the C flag during the calculation of Operand2, see Section 3.3.3 (p. 38)
• do not affect the V flag.
Move Top.
MOVT{cond} Rd, #imm16
where:
cond
Rd
imm16 is a 16#bit immediate constant.
MOVT writes a 16#bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register.
The write does not affect Rd[15:0].
The MOV, MOVT instruction pair enables you to generate any 32#bit constant.
Rd must not be SP and must not be PC.
This instruction does not change the flags.
Reverse bytes and Reverse bits.
op{cond} Rd, Rn
MOVS
MOV
MOVS
MOV
MOV
MVNS
MOVT
is an optional condition code, see Section 3.3.7 (p. 43) .
is the destination register.
R11, #0x000B
R1, #0xFA05
R10, R12
R3, #23
R8, SP
R2, #0xF
R3, #0xF123 ; Write 0xF123 to upper halfword of R3, lower halfword
; and APSR are unchanged
; Write value of 0x000B to R11, flags get updated
; Write value of 0xFA05 to R1, flags are not updated
; Write value in R12 to R10, flags get updated
; Write value of 23 to R3
; Write value of stack pointer to R8
; Write value of 0xFFFFFFF0 (bitwise inverse of 0xF)
; to the R2 and update flags
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