EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 97

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2011-02-04 - d0002_Rev1.00
See the register summary in Table 4.12 (p. 94) , and the Type descriptions in Table 4.15 (p. 97)
, for the ICSR attributes. The bit assignments are:
Table 4.15. ICSR bit assignments
31
Bits
[31]
[30:29]
[28]
[27]
[26]
30 29
Name
NMIPENDSET
-
PENDSVSET
PENDSVCLR
PENDSTSET
28
27 26
25
24
Type
RW
-
RW
WO
RW
23
22 21
Function
NMI set-pending bit.
Write:
0 = no effect1 = changes NMI exception state to pending.
Read:
0 = NMI exception is not pending
1 = NMI exception is pending.
Because NMI is the highest-priority exception, normally the processor enter the
NMI exception handler as soon as it registers a write of 1 to this bit, and entering
the handler clears this bit to 0. A read of this bit by the NMI exception handler
returns 1 only if the NMI signal is reasserted while the processor is executing that
handler.
Reserved.
PendSV set-pending bit.
Write:
0 = no effect1 = changes PendSV exception state to pending.
Read:
0 = PendSV exception is not pending
1 = PendSV exception is pending.
Writing 1 to this bit is the only way to set the PendSV exception state to pending.
PendSV clear-pending bit.
Write:
0 = no effect1 = removes the pending state from the PendSV exception.
SysTick exception set-pending bit.
Write:
0 = no effect1 = changes SysTick exception state to pending.
Read:
0 = SysTick exception is not pending
1 = SysTick exception is pending.
ISRPENDING
Reserved for Debug
Reserved
PENDSTCLR
PENDSTSET
PENDSVCLR
PENDSVSET
Reserved
NMIPENDSET
VECTPENDING
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97
12 11
10
9
Reserved
RETTOBASE
8
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VECTACTIVE
0