EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 34

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2011-02-04 - d0002_Rev1.00
Mnemonic
CLREX
CLZ
CMN, CMNS
CMP, CMPS
CPSID
CPSIE
DMB
DSB
EOR, EORS
ISB
IT
LDM
LDMDB,
LDMEA
LDMFD,
LDMIA
LDR
LDRB, LDRBT
LDRD
LDREX
LDREXB
LDREXH
LDRH, LDRHT
LDRSB,
LDRSBT
LDRSH,
LDRSHT
LDRT
LSL, LSLS
LSR, LSRS
Operands
-
Rd, Rm
Rn, Op2
Rn, Op2
iflags
iflags
-
-
{Rd,} Rn, Op2
-
-
Rn{!}, reglist
Rn{!}, reglist
Rn{!}, reglist
Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rt, Rt2, [Rn,
#offset]
Rt, [Rn, #offset]
Rt, [Rn]
Rt, [Rn]
Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rd, Rm, <Rs|#n>
Rd, Rm, <Rs|#n>
Brief description
Clear Exclusive
Count leading zeros
Compare Negative
Compare
Change Processor State, Disable Interrupts
Change Processor State, Enable Interrupts
Data Memory Barrier
Data Synchronization Barrier
Exclusive OR
Instruction Synchronization Barrier
If#Then condition block
Load Multiple registers, increment after
Load Multiple registers, decrement before
Load Multiple registers, increment after
Load Register with word
Load Register with byte
Load Register with two bytes
Load Register Exclusive
Load Register Exclusive with byte
Load Register Exclusive with halfword
Load Register with halfword
Load Register with signed byte
Load Register with signed halfword
Load Register with word
Logical Shift Left
Logical Shift Right
...the world's most energy friendly microcontrollers
34
Flags
-
-
N,Z,C,V
N,Z,C,V
-
-
-
-
N,Z,C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N,Z,C
N,Z,C
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Page
Section 3.4.9 (p.
56)
Section 3.5.4 (p.
61)
Section 3.5.5 (p.
62)
Section 3.5.5 (p.
62)
Section 3.10.2 (p.
80)
Section 3.10.2 (p.
80)
Section 3.10.3 (p.
81)
Section 3.10.4 (p.
82)
Section 3.5.2 (p.
59)
Section 3.10.5 (p.
82)
Section 3.9.3 (p.
76)
Section 3.4.6 (p.
52)
Section 3.4.6 (p.
52)
Section 3.4.6 (p.
52)
Section 3.4 (p.
45)
Section 3.4 (p.
45)
Section 3.4.2 (p.
46)
Section 3.4.8 (p.
54)
Section 3.4.8 (p.
54)
Section 3.4.8 (p.
54)
Section 3.4 (p.
45)
Section 3.4 (p.
45)
Section 3.4 (p.
45)
Section 3.4 (p.
45)
Section 3.5.3 (p.
60)
Section 3.5.3 (p.
60)