EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 101

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.3.8 Configuration and Control Register
2011-02-04 - d0002_Rev1.00
The CCR controls entry to Thread mode and enables:
• the handlers for NMI, hard fault and faults escalated by FAULTMASK to ignore bus faults
• trapping of divide by zero and unaligned accesses
• access to the STIR by unprivileged software, see Section 4.2.8 (p. 93) .
See the register summary in Table 4.12 (p. 94) for the CCR attributes.
The bit assignments are:
Table 4.20. CCR bit assignments
31
Bits
[4]
[3]
[2]
[1]
[0]
Bits
[31:10]
[9]
Name
SEVONPEND
-
SLEEPDEEP
SLEEPONEXIT
-
Name
-
STKALIGN
Function
Send Event on Pending bit:
0 = only enabled interrupts or events can wakeup the processor, disabled interrupts are
excluded1 = enabled events and all interrupts, including disabled interrupts, can wakeup the
processor.
When an event or interrupt enters pending state, the event signal wakes up the processor
from WFE. If the processor is not waiting for an event, the event is registered and affects the
next WFE.
The processor also wakes up on execution of an SEV instruction or an external event.
Reserved.
Controls whether the processor uses sleep or deep sleep as its low power mode:
0 = sleep
1 = deep sleep.
Indicates sleep-on-exit when returning from Handler mode to Thread mode:
0 = do not sleep when returning to Thread mode.
1 = enter sleep, or deep sleep, on return from an ISR.
Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main
application.
Reserved.
Reserved
Function
Reserved.
Indicates stack alignment on exception entry:
0 = 4-byte aligned1 = 8-byte aligned.
NONBASETHRDENA
...the world's most energy friendly microcontrollers
101
USERSETMPEND
UNALIGN_TRP
BFHFNMIGN
DIV_0_TRP
STKALIGN
Reserved
Reserved
10 9 8 7
www.energymicro.com
5 4 3 2 1 0