EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 11

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.1.3.5.4 Interruptible-continuable instructions
2.1.3.5.5 If-Then block
2.1.3.6 Exception mask registers
2.1.3.6.1 Priority Mask Register
2.1.3.6.2 Fault Mask Register
2011-02-04 - d0002_Rev1.00
handlers can examine EPSR value in the stacked PSR to indicate the operation that is at fault. See
Section 2.3.7 (p. 26)
When an interrupt occurs during the execution of an LDM or STM instruction, the processor:
• stops the load multiple or store multiple instruction operation temporarily
• stores the next register operand in the multiple operation to EPSR bits[15:12].
After servicing the interrupt, the processor:
• returns to the register pointed to by bits[15:12]
• resumes execution of the multiple load or store instruction.
When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.
The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruction in
the block is conditional. The conditions for the instructions are either all the same, or some can be the
inverse of others. See Section 3.9.3 (p. 76) for more information.
The exception mask registers disable the handling of exceptions by the processor. Disable exceptions
where they might impact on timing critical tasks.
To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to
change the value of PRIMASK or FAULTMASK. See Section 3.10.6 (p. 83) , Section 3.10.7 (p. 83)
, and Section 3.10.2 (p. 80) for more information.
The PRIMASK register prevents activation of all exceptions with configurable priority. See the register
summary in Table 2.2 (p. 7) for its attributes. The bit assignments are:
Table 2.7. PRIMASK register bit assignments
The FAULTMASK register prevents activation of all exceptions except for Non-Maskable Interrupt (NMI).
See the register summary in Table 2.2 (p. 7) for its attributes. The bit assignments are:
31
Bits
[31:1]
[0]
Name
-
PRIMASK
Function
Reserved
0 = no effect
1 = prevents the activation of all exceptions with configurable priority.
Reserved
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PRIMASK
1 0