EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 54

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.4.7.2 Operation
3.4.7.3 Restrictions
3.4.7.4 Condition flags
3.4.7.5 Examples
3.4.8 LDREX and STREX
3.4.8.1 Syntax
2011-02-04 - d0002_Rev1.00
PUSH and POP are synonyms for STMDB and LDM (or LDMIA) with the memory addresses for the access
based on SP, and with the final address for the access written back to the SP. PUSH and POP are the
preferred mnemonics in these cases.
PUSH stores registers on the stack in order of decreasing the register numbers, with the highest
numbered register using the highest memory address and the lowest numbered register using the lowest
memory address.
POP loads registers from the stack in order of increasing register numbers, with the lowest numbered
register using the lowest memory address and the highest numbered register using the highest memory
address.
See Section 3.4.6 (p. 52) for more information.
In these instructions:
• reglist must not contain SP
• for the PUSH instruction, reglist must not contain PC
• for the POP instruction, reglist must not contain PC if it contains LR.
When PC is in reglist in a POP instruction:
• bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this
• if the instruction is conditional, it must be the last instruction in the IT block.
These instructions do not change the flags.
Load and Store Register Exclusive.
LDREX{cond} Rt, [Rn {, #offset}]
STREX{cond} Rd, Rt, [Rn {, #offset}]
LDREXB{cond} Rt, [Rn]
STREXB{cond} Rd, Rt, [Rn]
LDREXH{cond} Rt, [Rn]
halfword-aligned address
PUSH
PUSH
POP
{R0,R4#R7}
{R2,LR}
{R0,R10,PC}
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