EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 30

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.4.4 Lockup
2.5 Power management
2.5.1 Entering sleep mode
2.5.1.1 Wait for interrupt
2.5.1.2 Wait for event
2011-02-04 - d0002_Rev1.00
Table 2.18. Fault status and fault address registers
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers.
When the processor is in lockup state it does not execute any instructions. The processor remains in
lockup state until either:
• it is reset
• an NMI occurs.
Note
The Cortex-M3 processor sleep modes reduce power consumption:
• Sleep mode (Energy Mode 1) stops the processor clock
• Deep sleep mode (Energy Mode 2/3) stops the high frequency oscillators and HFPERCLK/
The SLEEPDEEP bit of the SCR selects which sleep mode is used, see Section 4.3.7 (p. 100) . For
more information about the behavior of the sleep modes see the EMU documentation in the reference
manual for the device.
This section describes the mechanisms for entering sleep mode, and the conditions for waking up from
sleep mode.
This section describes the mechanisms software can use to put the processor into sleep mode.
The system can generate spurious wakeup events, for example a debug operation wakes up the
processor. Therefore software must be able to put the processor back into sleep mode after such an
event. A program might have an idle loop to put the processor back to sleep mode.
The wait for interrupt instruction, WFI, causes immediate entry to sleep mode. When the processor
executes a WFI instruction it stops executing instructions and enters sleep mode. See Section 3.10.12 (p.
86) for more information.
The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of an one-bit
event register. When the processor executes a WFE instruction, it checks this register:
Handler
Hard fault
Memory management
fault
Bus fault
Usage fault
HFCORECLK as well as flash memory.
If lockup state occurs from the NMI handler a subsequent NMI does not cause the
processor to leave lockup state.
Status register
name
HFSR
MMFSR
BFSR
UFSR
Address register
name
-
MMFAR
BFAR
-
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Register description
Section 4.3.12 (p. 109)
Section 4.3.11.1 (p. 105)
Section 4.3.13 (p. 110)
Section 4.3.11.2 (p. 107)
Section 4.3.14 (p. 110)
Section 4.3.11.3 (p. 108)
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