EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 60

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.5.2.4 Condition flags
3.5.2.5 Examples
3.5.3 ASR, LSL, LSR, ROR, and RRX
3.5.3.1 Syntax
3.5.3.2 Operation
2011-02-04 - d0002_Rev1.00
If S is specified, these instructions:
• update the N and Z flags according to the result
• can update the C flag during the calculation of Operand2, see Section 3.3.3 (p. 38)
• do not affect the V flag.
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend.
op{S}{cond} Rd, Rm, Rs
op{S}{cond} Rd, Rm, #n
RRX{S}{cond} Rd, Rm
where:
op is one of:
S
Rd is the destination register.
Rm is the register holding the value to be shifted.
Rs is the register holding the shift length to apply to the value in Rm. Only the least significant byte is
n
Note
ASR, LSL, LSR, and ROR move the bits in the register Rm to the left or right by the number of places
specified by constant n or register Rs.
AND
ORREQ
ANDS
EORS
BIC
ORN
ORNS
ASR Arithmetic Shift Right.
LSL Logical Shift Left.
LSR Logical Shift Right.
ROR Rotate Right.
is an optional suffix. If S is specified, the condition code flags are updated on the result of the
operation, see Section 3.3.7 (p. 43) .
used and can be in the range 0 to 255.
is the shift length. The range of shift length depends on the instruction:
ASR shift length from 1 to 32
LSL shift length from 0 to 31
LSR shift length from 1 to 32
ROR shift length from 1 to 31.
MOV{S}{cond} Rd, Rm is the preferred syntax for LSL{S}{cond} Rd, Rm, #0.
R9, R2, #0xFF00
R2, R0, R5
R9, R8, #0x19
R7, R11, #0x18181818
R0, R1, #0xab
R7, R11, R14, ROR #4
R7, R11, R14, ASR #32
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