EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 79

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.9.4.4 Condition flags
3.9.4.5 Examples
3.10 Miscellaneous instructions
2011-02-04 - d0002_Rev1.00
• Rm must not be SP and must not be PC
• when any of these instructions is used inside an IT block, it must be the last instruction of the IT block.
These instructions do not change the flags.
Case1
; an instruction sequence follows
Case2
; an instruction sequence follows
Case3
; an instruction sequence follows
BranchTable_Byte
BranchTable_H
CaseA
; an instruction sequence follows
CaseB
; an instruction sequence follows
CaseC
; an instruction sequence follows
Table 3.13 (p. 79) shows the remaining Cortex-M3 instructions:
Table 3.13. Miscellaneous instructions
Mnemonic
BKPT
CPSID
CPSIE
DMB
DSB
ISB
ADR.W
TBB
DCB
DCB
DCB
TBH
DCI
DCI
DCI
[R0, R1]
R0, BranchTable_Byte
0
((Case2-Case1)/2)
((Case3-Case1)/2)
[PC, R1, LSL #1]
((CaseA - BranchTable_H)/2)
((CaseB - BranchTable_H)/2)
((CaseC - BranchTable_H)/2)
Brief description
Breakpoint
Change Processor State, Disable Interrupts
Change Processor State, Enable Interrupts
Data Memory Barrier
Data Synchronization Barrier
Instruction Synchronization Barrier
; R1 is the index, R0 is the base address of the
; branch table
; Case1 offset calculation
; Case2 offset calculation
; Case3 offset calculation
; R1 is the index, PC is used as base of the
; branch table
; CaseA offset calculation
; CaseB offset calculation
; CaseC offset calculation
See
Section 3.10.1 (p.
80)
Section 3.10.2 (p.
80)
Section 3.10.2 (p.
80)
Section 3.10.3 (p.
81)
Section 3.10.4 (p.
82)
Section 3.10.5 (p.
82)
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