EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 20

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.2.5.2 Directly accessing a bit-band region
2.2.6 Memory endianness
2.2.6.1 Little-endian format
2.2.7 Synchronization primitives
2011-02-04 - d0002_Rev1.00
Bits[31:1] of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as writing
0xFF. Writing 0x00 has the same effect as writing 0x0E.
Reading a word in the alias region:
• 0x00000000 indicates that the targeted bit in the bit-band region is set to zero
• 0x00000001 indicates that the targeted bit in the bit-band region is set to 1
Section 2.2.3 (p. 16) describes the behavior of direct byte, halfword, or word accesses to the bit-
band regions.
The processor views memory as a linear collection of bytes numbered in ascending order from
zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word.
Section 2.2.6.1 (p. 20) describes how words of data are stored in memory.
The EFM32 uses a little-endian format, in which the processor stores the least significant byte of a word
at the lowest-numbered byte, and the most significant byte at the highest-numbered byte. For example:
The Cortex-M3 instruction set includes pairs of synchronization primitives. These provide a non-blocking
mechanism that a thread or process can use to obtain exclusive access to a memory location. Software
can use them to perform a guaranteed read-modify-write memory update sequence, or for a semaphore
mechanism.
A pair of synchronization primitives comprises:
A Load-Exclusive instruction
A Store-Exclusive instruction
The pairs of Load-Exclusive and Store-Exclusive instructions are:
Address A
A+ 1
A+ 2
A+ 3
7
Mem ory
B0
B1
B2
B3
0
lsbyte
m sbyte
31
Used to read the value of a memory location, requesting exclusive
access to that location.
Used to attempt to write to the same memory location, returning a
status bit to a register. If this bit is:
0 it indicates that the thread or process gained exclusive access to
1 it indicates that the thread or process did not gain exclusive
B3
the memory, and the write succeeds,
access to the memory, and no write is performed,
2423
B2
...the world's most energy friendly microcontrollers
Register
20
1615
B1
8 7
B0
0
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