EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 83

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.10.6 MRS
3.10.6.1 Syntax
3.10.6.2 Operation
3.10.6.3 Restrictions
3.10.6.4 Condition flags
3.10.6.5 Examples
3.10.7 MSR
3.10.7.1 Syntax
2011-02-04 - d0002_Rev1.00
Move the contents of a special register to a general#purpose register.
MRS{cond} Rd, spec_reg
where:
cond
Rd
spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK,
Use MRS in combination with MSR as part of a read#modify#write sequence for updating a PSR, for
example to clear the Q flag.
In process swap code, the programmers model state of the process being swapped out must be saved,
including relevant PSR contents. Similarly, the state of the process being swapped in must also be
restored. These operations use MRS in the state-saving instruction sequence and MSR in the state-
restoring instruction sequence.
Note
See Section 3.10.7 (p. 83) .
Rd must not be SP and must not be PC.
This instruction does not change the flags.
Move the contents of a general#purpose register into the specified special register.
MSR{cond} spec_reg, Rn
where:
cond
ISB
MRS
; Instruction Synchronisation Barrier
R0, PRIMASK ; Read PRIMASK value and write it to R0
BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction.
is an optional condition code, see Section 3.3.7 (p. 43) .
is the destination register.
BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.
is an optional condition code, see Section 3.3.7 (p. 43) .
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