EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 108

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.3.11.3 Usage Fault Status Register
2011-02-04 - d0002_Rev1.00
The UFSR indicates the cause of a usage fault. The bit assignments are:
Table 4.28. UFSR bit assignments
15
Bits
[0]
Bits
[15:10]
[9]
[8]
[7:4]
[3]
[2]
DIVBYZERO
UNALIGNED
Reserved
Name
IBUSERR
Name
-
DIVBYZERO
UNALIGNED
-
NOCP
INVPC
10 9 8 7
Function
1 = a data bus error has occurred, and the PC value stacked for the exception return points to
the instruction that caused the fault.
When the processor sets this bit is 1, it writes the faulting address to the BFAR.
Instruction bus error:
0 = no instruction bus error
1 = instruction bus error.
The processor detects the instruction bus error on prefetching an instruction, but it sets the
IBUSERR flag to 1 only if it attempts to issue the faulting instruction.
When the processor sets this bit is 1, it does not write a fault address to the BFAR.
UNDEFINSTR
Function
Reserved.
Divide by zero usage fault:
0 = no divide by zero fault, or divide by zero trapping not enabled
1 = the processor has executed an SDIV or UDIV instruction with a divisor of 0.
When the processor sets this bit to 1, the PC value stacked for the exception return points to
the instruction that performed the divide by zero.
Enable trapping of divide by zero by setting the DIV_0_TRP bit in the CCR to 1, see
Section 4.3.8 (p. 101) .
Unaligned access usage fault:
0 = no unaligned access fault, or unaligned access trapping not enabled
1 = the processor has made an unaligned memory access.
Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the CCR to 1, see
Section 4.3.8 (p. 101) .
Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of
UNALIGN_TRP.
Reserved.
No coprocessor usage fault. The processor does not support coprocessor instructions:
0 = no usage fault caused by attempting to access a coprocessor
1 = the processor has attempted to access a coprocessor.
Invalid PC load usage fault, caused by an invalid PC load by EXC_RETURN:
0 = no invalid PC load usage fault
1 = the processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an
invalid context, or an invalid EXC_RETURN value.
INVSTATE
Reserved
INVPC
NOCP
4 3 2 1 0
...the world's most energy friendly microcontrollers
108
www.energymicro.com