EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 72

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.8.1.5 Examples
3.8.2 SBFX and UBFX
3.8.2.1 Syntax
3.8.2.2 Operation
3.8.2.3 Restrictions
3.8.2.4 Condition flags
3.8.2.5 Examples
3.8.3 SXT and UXT
3.8.3.1 Syntax
2011-02-04 - d0002_Rev1.00
Signed Bit Field Extract and Unsigned Bit Field Extract.
SBFX{cond} Rd, Rn, #lsb, #width
UBFX{cond} Rd, Rn, #lsb, #width
where:
cond
Rd
Rn
lsb
width is the width of the bitfield and must be in the range 1 to 32#lsb.
SBFX extracts a bitfield from one register, sign extends it to 32 bits, and writes the result to the destination
register.
UBFX extracts a bitfield from one register, zero extends it to 32 bits, and writes the result to the destination
register.
Do not use SP and do not use PC.
These instructions do not affect the flags.
Sign extend and Zero extend.
SXTextend{cond} {Rd,} Rm {, ROR #n}
SBFX
UBFX
BFC
BFI
R0, R1, #20, #4
R8, R11, #9, #10 ; Extract bit 9 to bit 18 (10 bits) from R11 and zero
is an optional condition code, see Section 3.3.7 (p. 43) .
is the destination register.
is the source register.
is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31.
R4, #8, #12
R9, R2, #8, #12
; Extract bit 20 to bit 23 (4 bits) from R1 and sign
; extend to 32 bits and then write the result to R0.
; extend to 32 bits and then write the result to R8
; Clear bit 8 to bit 19 (12 bits) of R4 to 0
; Replace bit 8 to bit 19 (12 bits) of R9 with
; bit 0 to bit 11 from R2
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