EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 26

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.3.6 Interrupt priority grouping
2.3.7 Exception entry and return
2011-02-04 - d0002_Rev1.00
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means
that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed
before IRQ[0].
If multiple pending exceptions have the same priority, the pending exception with the lowest exception
number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same
priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a higher
priority exception occurs. If an exception occurs with the same priority as the exception being handled,
the handler is not preempted, irrespective of the exception number. However, the status of the new
interrupt changes to pending.
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This divides
each interrupt priority register entry into two fields:
• an upper field that defines the group priority
• a lower field that defines a subpriority within the group.
Only the group priority determines preemption of interrupt exceptions. When the processor is executing
an interrupt exception handler, another interrupt with the same group priority as the interrupt being
handled does not preempt the handler,
If multiple pending interrupts have the same group priority, the subpriority field determines the order in
which they are processed. If multiple pending interrupts have the same group priority and subpriority,
the interrupt with the lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see
Section 4.3.6 (p. 99) .
Descriptions of exception handling use the following terms:
Preemption
Return
Tail-chaining
Late-arriving
When the processor is executing an exception handler, an exception can preempt
the exception handler if its priority is higher than the priority of the exception being
handled. See Section 2.3.6 (p. 26) for more information about preemption by
an interrupt.
When one exception preempts another, the exceptions are called nested
exceptions. See Section 2.3.7.1 (p. 27) more information.
This occurs when the exception handler is completed, and:
• there is no pending exception with sufficient priority to be serviced
• the completed exception handler was not handling a late-arriving exception.
The processor pops the stack and restores the processor state to the state it had
before the interrupt occurred. See Section 2.3.7.2 (p. 27) for more information.
This mechanism speeds up exception servicing. On completion of an exception
handler, if there is a pending exception that meets the requirements for exception
entry, the stack pop is skipped and control transfers to the new exception handler.
This mechanism speeds up preemption. If a higher priority exception occurs during
state saving for a previous exception, the processor switches to handle the higher
priority exception and initiates the vector fetch for that exception. State saving is not
affected by late arrival because the state saved is the same for both exceptions.
Therefore the state saving continues uninterrupted. The processor can accept a late
arriving exception until the first instruction of the exception handler of the original
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