EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 100

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.3.6.1 Binary point
4.3.7 System Control Register
2011-02-04 - d0002_Rev1.00
The PRIGROUP field indicates the position of the binary point that splits the PRI_n fields in the Interrupt
Priority Registers into separate group priority and subpriority fields. Table 4.18 (p. 100) shows how
the PRIGROUP value controls this split.
Table 4.18. Priority grouping
1
Note
The SCR controls features of entry to and exit from low power state. See the register summary in
Table 4.12 (p. 94) for its attributes. The bit assignments are:
Table 4.19. SCR bit assignments
31
PRI_n[7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a subpriority field bit.
Bits
[2]
[1]
[0]
PRIGROUP
b100-b000
b101
b110
b111
Bits
[31:5]
Name
-
Name
SYSRESETREQ
VECTCLRACTIVE
VECTRESET
Determining preemption of an exception uses only the group priority field, see
Section 2.3.6 (p. 26) .
Interrupt priority level value, PRI_N[7:0]
Binary point
bxxx.00000
bxx.y00000
bx.yy00000
b.yyy00000
1
Function
Reserved.
Group priority bits
[7:5]
[7:6]
[7]
None
Type
WO
WO
WO
Function
System reset request:
0 = no system reset request
1 = asserts a signal to the EFM32 Reset Managment Unit (RMU) to
request a reset.
This is intended to force a large system reset of all major components
except for debug.
This bit reads as 0.
Reserved for Debug use. This bit reads as 0. When writing to the register
you must write 0 to this bit, otherwise behavior is Unpredictable.
Reserved for Debug use. This bit reads as 0. When writing to the register
you must write 0 to this bit, otherwise behavior is Unpredictable.
Reserved
Subpriority bits
None
[5]
[6:5]
[7:5]
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100
Number of
Group priorities
8
4
2
1
SLEEPONEXIT
SEVONPEND
SLEEPDEEP
Reserved
Reserved
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Subpriorities
1
2
4
8
5
4 3 2 1 0