EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 39

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.3.3.1.1 Instruction substitution
3.3.3.2 Register with optional shift
3.3.4 Shift Operations
2011-02-04 - d0002_Rev1.00
#constant
where constant can be:
• any constant that can be produced by shifting an 8#bit value left by any number of bits within a 32#bit
• any constant of the form 0x00XY00XY
• any constant of the form 0xXY00XY00
• any constant of the form 0xXYXYXYXY.
Note
In addition, in a small number of instructions, constant can take a wider range of values. These are
described in the individual instruction descriptions.
When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS,
TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and
can be produced by shifting an 8-bit value. These instructions do not affect the carry flag if Operand2
is any other constant.
Your assembler might be able to produce an equivalent instruction in cases where you specify a constant
that is not permitted. For example, an assembler might assemble the instruction CMP Rd, #0xFFFFFFFE
as the equivalent instruction CMN Rd, #0x2.
You specify an Operand2 register in the form:
Rm {, shift}
where:
Rm
shift is an optional shift to be applied to Rm. It can be one of:
If you omit the shift, or specify LSL #0, the instruction uses the value in Rm.
If you specify a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is used by the
instruction. However, the contents in the register Rm remains unchanged. Specifying a register with shift
also updates the carry flag when used with certain instructions. For information on the shift operations
and how they affect the carry flag, see Section 3.3.4 (p. 39)
Register shift operations move the bits in a register left or right by a specified number of bits, the shift
length. Register shift can be performed:
word
is the register holding the data for the second operand.
ASR #n
LSL #n
LSR #n
ROR #n
RRX
-
In the constants shown above, X and Y are hexadecimal digits.
arithmetic shift right n bits, 1 # n # 32.
logical shift left n bits, 1 # n # 31.
logical shift right n bits, 1 # n # 32.
rotate right n bits, 1 # n # 31.
rotate right one bit, with extend.
if omitted, no shift occurs, equivalent to LSL #0.
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