EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 59

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.5.1.6 Multiword arithmetic examples
3.5.2 AND, ORR, EOR, BIC, and ORN
3.5.2.1 Syntax
3.5.2.2 Operation
3.5.2.3 Restrictions
2011-02-04 - d0002_Rev1.00
Example 3.4 (p. 59) shows two instructions that add a 64#bit integer contained in R2 and R3 to
another 64#bit integer contained in R0 and R1, and place the result in R4 and R5.
Example 3.4. 64-bit addition
Multiword values do not have to use consecutive registers. Example 3.5 (p. 59) shows instructions
that subtract a 96#bit integer contained in R9, R1, and R11 from another contained in R6, R2, and R8.
The example stores the result in R6, R9, and R2.
Example 3.5. 96-bit subtraction
Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT.
op{S}{cond} {Rd,} Rn, Operand2
where:
op
S
cond
Rd
Rn
Operand2 is a flexible second operand. See Section 3.3.3 (p. 38) for details of the options.
The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations on the
values in Rn and Operand2.
The BIC instruction performs an AND operation on the bits in Rn with the complements of the
corresponding bits in the value of Operand2.
The ORN instruction performs an OR operation on the bits in Rn with the complements of the
corresponding bits in the value of Operand2.
Do not use SP and do not use PC.
ADDS
ADC
SUBS
SBCS
SBC
is one of:
AND logical AND.
ORR logical OR, or bit set.
EOR logical Exclusive OR.
BIC logical AND NOT, or bit clear.
ORN logical OR NOT.
is an optional suffix. If S is specified, the condition code flags are updated on the result of
the operation, see Section 3.3.7 (p. 43) .
is an optional condition code, see Section 3.3.7 (p. 43) .
is the destination register.
is the register holding the first operand.
R4, R0, R2
R5, R1, R3
R6, R6, R9
R9, R2, R1
R2, R8, R11
; add the least significant words
; add the most significant words with carry
; subtract the least significant words
; subtract the middle words with carry
; subtract the most significant words with carry
...the world's most energy friendly microcontrollers
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