EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 115

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.5.2 MPU Control Register
2011-02-04 - d0002_Rev1.00
Table 4.39. TYPE register bit assignments
The MPU CTRL register:
• enables the MPU
• enables the default memory map background region
• enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK
See the register summary in Table 4.38 (p. 114) for the MPU CTRL attributes. The bit assignments are:
Table 4.40. MPU CTRL register bit assignments
31
31
Bits
[31:24]
[23:16]
[15:8]
[7:0]
[0]
Bits
[31:3]
[2]
[1]
escalated handlers.
Name
-
PRIVDEFENA
HFNMIENA
Reserved
Name
-
IREGION
DREGION
-
SEPARATE
Function
Reserved.
Indicates the number of supported MPU instruction regions.
Always contains 0x00. The MPU memory map is unified and is described by the DREGION field.
Indicates the number of supported MPU data regions:
0x08 = Eight MPU regions.
Reserved.
Indicates support for unified or separate instruction and date memory maps:
0 = unified.
Function
Reserved.
Enables privileged software access to the default memory map:
0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a
location not covered by any enabled region causes a fault.
1 = If the MPU is enabled, enables use of the default memory map as a background region for
privileged software accesses.
When enabled, the background region acts as if it is region number -1. Any region that is
defined and enabled has priority over this default map.
If the MPU is disabled, the processor ignores this bit.
Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers.
When the MPU is enabled:
24 23
IREGION
Reserved
16 15
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115
DREGION
8 7
PRIVDEFENA
HFNMIENA
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ENABLE
Reserved
SEPARATE
3
2
1 0
1 0