EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 118

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.5.5.1 SIZE field values
2011-02-04 - d0002_Rev1.00
RASR is accessible using word or halfword accesses:
• the most significant halfword holds the region attributes
• the least significant halfword holds the region size and the region and subregion enable bits.
The bit assignments are:
Table 4.43. RASR bit assignments
For information about access permission, see Section 4.5.6 (p. 119) .
The SIZE field defines the size of the MPU memory region specified by the RNR. as follows:
The smallest permitted region size is 32B, corresponding to a SIZE value of 4. Table 4.44 (p. 118)
gives example SIZE values, with the corresponding region size and value of N in the RBAR.
Table 4.44. Example SIZE field values
31
Bits
[31:29]
[28]
[27]
[26:24]
[23:22]
[21:19, 17, 16]
[18]
[15:8]
[7:6]
[5:1]
[0]
SIZE value
b00100 (4)
(Region size in bytes) = 2
29 28 27 26
Region size
32B
Name
-
XN
-
AP
-
TEX, C, B
S
SRD
-
SIZE
ENABLE
Reserved
XN
Reserved
AP
24 23 22 21
Function
Reserved.
Instruction access disable bit:
0 = instruction fetches enabled1 = instruction fetches disabled.
Reserved.
Access permission field, see Table 4.47 (p. 120) .
Reserved.
Memory access attributes, see Table 4.45 (p. 119) .
Shareable bit, see Table 4.45 (p. 119) .
Subregion disable bits. For each bit in this field:
0 = corresponding sub-region is enabled
1 = corresponding sub-region is disabled
See Section 4.5.8.3 (p. 122) for more information.
Region sizes of 128 bytes and less do not support subregions. When writing the attributes
for such a region, write the SRD field as 0x00.
Reserved.
Specifies the size of the MPU protection region. The minimum permitted value is 3
(b00010), see See Section 4.5.5.1 (p. 118) for more information.
Region enable bit.
Value of N
5
(SIZE+1)
Reserved
TEX
1
19 18 17 16 15
Note
Minimum permitted size
S C B
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118
SRD
Reserved
ENABLE
8 7 6 5
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SIZE
1 0