EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 66

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.5.9.2 Operation
3.5.9.3 Restrictions
3.5.9.4 Condition flags
3.5.9.5 Examples
3.6 Multiply and divide instructions
2011-02-04 - d0002_Rev1.00
These instructions test the value in a register against Operand2. They update the condition flags based
on the result, but do not write the result to a register.
The TST instruction performs a bitwise AND operation on the value in Rn and the value of Operand2.
This is the same as the ANDS instruction, except that it discards the result.
To test whether a bit of Rn is 0 or 1, use the TST instruction with an Operand2 constant that has that
bit set to 1 and all other bits cleared to 0.
The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the value of
Operand2. This is the same as the EORS instruction, except that it discards the result.
Use the TEQ instruction to test if two values are equal without affecting the V or C flags.
TEQ is also useful for testing the sign of a value. After the comparison, the N flag is the logical Exclusive
OR of the sign bits of the two operands.
Do not use SP and do not use PC.
These instructions:
• update the N and Z flags according to the result
• can update the C flag during the calculation of Operand2, see Section 3.3.3 (p. 38)
• do not affect the V flag.
Table 3.9 (p. 66) shows the multiply and divide instructions:
Table 3.9. Multiply and divide instructions
Mnemonic
MLA
MLS
MUL
SDIV
SMLAL
SMULL
UDIV
UMLAL
TST
TEQEQ
Brief description
Multiply with Accumulate, 32-bit result
Multiply and Subtract, 32-bit result
Multiply, 32-bit result
Signed Divide
Signed Multiply with Accumulate
(32x32+64), 64-bit result
Signed Multiply (32x32), 64-bit result
Unsigned Divide
Unsigned Multiply with Accumulate
(32x32+64), 64-bit result
R0, #0x3F8
R10, R9
; Perform bitwise AND of R0 value to 0x3F8,
; APSR is updated but result is discarded
; Conditionally test if value in R10 is equal to
; value in R9, APSR is updated but result is discarded
See
Section 3.6.1 (p. 67)
Section 3.6.1 (p. 67)
Section 3.6.1 (p. 67)
Section 3.6.3 (p. 69)
Section 3.6.2 (p. 68)
Section 3.6.2 (p. 68)
Section 3.6.3 (p. 69)
Section 3.6.2 (p. 68)
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