EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 124

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Glossary
This glossary describes some of the terms used in technical documents from ARM.
Abort
Aligned
Banked register
Base register
Big-endian (BE)
Big-endian memory
Breakpoint
Byte-invariant
Cache
2011-02-04 - d0002_Rev1.00
A mechanism that indicates to a processor that the value associated with a
memory access is invalid. An abort can be caused by the external or internal
memory system as a result of attempting to access invalid instruction or data
memory.
A data item stored at an address that is divisible by the number of bytes that
defines the data size is said to be aligned. Aligned words and halfwords have
addresses that are divisible by four and two respectively. The terms word-
aligned and halfword-aligned therefore stipulate addresses that are divisible
by four and two respectively.
A register that has multiple physical copies, where the state of the processor
determines which copy is used. The Stack Pointer, SP (R13) is a banked
register.
In instruction descriptions, a register specified by a load or store instruction
that is used to hold the base value for the instruction’s address calculation.
Depending on the instruction and its addressing mode, an offset can be
added to or subtracted from the base register value to form the address that
is sent to memory.
See Also Index register.
Byte ordering scheme in which bytes of decreasing significance in a data
word are stored at increasing addresses in memory.
See Also Byte-invariant, Endianness, Little-endian.
Memory in which:
• a byte or halfword at a word-aligned address is the most significant byte
• a byte at a halfword-aligned address is the most significant byte within the
See Also Little-endian memory.
A breakpoint is a mechanism provided by debuggers to identify an instruction
at which program execution is to be halted. Breakpoints are inserted by the
programmer to enable inspection of register contents, memory locations,
variable values at fixed points in the program execution to test that the
program is operating correctly. Breakpoints are removed after the program
is successfully tested.
In a byte-invariant system, the address of each byte of memory remains
unchanged when switching between little-endian and big-endian operation.
When a data item larger than a byte is loaded from or stored to memory,
the bytes making up that data item are arranged into the correct order
depending on the endianness of the memory access. An ARM byte-
invariant implementation also supports unaligned halfword and word memory
accesses. It expects multi-word accesses to be word-aligned.
A block of on-chip or off-chip fast access memory locations, situated between
the processor and main memory, used for storing and retrieving copies of
often used instructions, data, or instructions and data. This is done to greatly
or halfword within the word at that address
halfword at that address.
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