EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 125

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Condition field
Conditional execution
Context
Coprocessor
Debugger
Direct Memory Access
(DMA)
Doubleword
Doubleword-aligned
Endianness
Exception
Exception service routine
Exception vector
Flat address mapping
Halfword
Illegal instruction
Implementation-defined
2011-02-04 - d0002_Rev1.00
increase the average speed of memory accesses and so improve processor
performance.
A four-bit field in an instruction that specifies a condition under which the
instruction can execute.
If the condition code flags indicate that the corresponding condition is true
when the instruction starts executing, it executes normally. Otherwise, the
instruction does nothing.
The environment that each process operates in for a multitasking operating
system. In ARM processors, this is limited to mean the physical address
range that it can access in memory and the associated memory access
permissions.
A processor that supplements the main processor. Cortex-M3 does not
support any coprocessors.
A debugging system that includes a program, used to detect, locate, and
correct software faults, together with custom hardware that supports software
debugging.
An operation that accesses main memory directly, without the processor
performing any accesses to the data concerned.
A 64-bit data item. The contents are taken as being an unsigned integer
unless otherwise stated.
A data item having a memory address that is divisible by eight.
Byte ordering. The scheme that determines the order that successive bytes
of a data word are stored in memory. An aspect of the system’s memory
mapping.
See Also Little-endian and Big-endian.
An event that interrupts program execution. When an exception occurs,
the processor suspends the normal program flow and starts execution at
the address indicated by the corresponding exception vector. The indicated
address contains the first instruction of the handler for the exception.
An exception can be an interrupt request, a fault, or a software-generated
system exception. Faults include attempting an invalid memory access,
attempting to execute an instruction in an invalid processor state, and
attempting to execute an undefined instruction.
See Interrupt handler.
See Interrupt vector.
A system of organizing memory in which each physical address in the
memory space is the same as the corresponding virtual address.
A 16-bit data item.
An instruction that is architecturally Undefined.
The behavior is not architecturally defined, but is defined and documented
by individual implementations.
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