EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 61

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.5.3.3 Restrictions
3.5.3.4 Condition flags
3.5.3.5 Examples
3.5.4 CLZ
3.5.4.1 Syntax
3.5.4.2 Operation
3.5.4.3 Restrictions
3.5.4.4 Condition flags
3.5.4.5 Examples
2011-02-04 - d0002_Rev1.00
RRX moves the bits in register Rm to the right by 1.
In all these instructions, the result is written to Rd, but the value in register Rm remains unchanged. For
details on what result is generated by the different instructions, see Section 3.3.4 (p. 39) .
Do not use SP and do not use PC.
If S is specified:
• these instructions update the N and Z flags according to the result
• the C flag is updated to the last bit shifted out, except when the shift length is 0, see Section 3.3.4 (p.
Count Leading Zeros.
CLZ{cond} Rd, Rm
where:
cond is an optional condition code, see Section 3.3.7 (p. 43) .
Rd
Rm
The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd.
The result value is 32 if no bits are set in the source register, and zero if bit[31] is set.
Do not use SP and do not use PC.
This instruction does not change the flags.
39) .
ASR
LSLS
LSR
ROR
RRX
CLZ
CLZNE
is the destination register.
is the operand register.
R7, R8, #9
R1, R2, #3
R4, R5, #6
R4, R5, R6
R4, R5
R4,R9
R2,R3
; Arithmetic shift right by 9 bits
; Logical shift left by 3 bits with flag update
; Logical shift right by 6 bits
; Rotate right by the value in the bottom byte of R6
; Rotate right with extend
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