EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 45

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.3.8 Instruction width selection
3.4 Memory access instructions
2011-02-04 - d0002_Rev1.00
Example 3.2 (p. 45) shows the use of conditional instructions to update the value of R4 if the signed
values R0 is greater than R1 and R2 is greater than R3.
Example 3.2. Compare and update value
There are many instructions that can generate either a 16-bit encoding or a 32-bit encoding depending on
the operands and destination register specified. For some of these instructions, you can force a specific
instruction size by using an instruction width suffix. The .W suffix forces a 32-bit instruction encoding.
The .N suffix forces a 16-bit instruction encoding.
If you specify an instruction width suffix and the assembler cannot generate an instruction encoding of
the requested width, it generates an error.
Note
To use an instruction width suffix, place it immediately after the instruction mnemonic and condition
code, if any. Example 3.3 (p. 45) shows instructions with the instruction width suffix.
Example 3.3. Instruction width selection
Table 3.5 (p. 45) shows the memory access instructions:
Table 3.5. Memory access instructions
Mnemonic
ADR
CLREX
LDM{mode}
LDR{type}
LDR{type}
LDR{type}T
LDR
LDREX{type} Load Register Exclusive
POP
PUSH
STM{mode}
STR{type}
CMP
ITT
CMPGT
MOVGT
BCS.W
ADDS.W R0, R0, R1 ; creates a 32-bit instruction even though the same
In some cases it might be necessary to specify the .W suffix, for example if the operand
is the label of an instruction or literal data, as in the case of branch instructions. This is
because the assembler might not automatically generate the right size encoding.
label
Brief description
Load PC-relative address
Clear Exclusive
Load Multiple registers
Load Register using immediate offset
Load Register using register offset
Load Register with unprivileged access
Load Register using PC-relative address
Pop registers from stack
Push registers onto stack
Store Multiple registers
Store Register using immediate offset
R0, R1
GT
R2, R3
R4, R5
; creates a 32-bit instruction even for a short branch
; operation can be done by a 16-bit instruction
; Compare R0 and R1, setting flags
; IT instruction for the two GT conditions
; If 'greater than', compare R2 and R3, setting flags
; If still 'greater than', do R4 = R5
See
Section 3.4.1 (p. 46)
Section 3.4.9 (p. 56)
Section 3.4.6 (p. 52)
Section 3.4.2 (p. 46)
Section 3.4.3 (p. 48)
Section 3.4.4 (p. 50)
Section 3.4.5 (p. 51)
Section 3.4.8 (p. 54)
Section 3.4.7 (p. 53)
Section 3.4.7 (p. 53)
Section 3.4.6 (p. 52)
Section 3.4.2 (p. 46)
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