EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 46

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.4.1 ADR
3.4.1.1 Syntax
3.4.1.2 Operation
3.4.1.3 Restrictions
3.4.1.4 Condition flags
3.4.1.5 Examples
3.4.2 LDR and STR, immediate offset
3.4.2.1 Syntax
2011-02-04 - d0002_Rev1.00
Load PC-relative address.
ADR{cond} Rd, label
where:
cond
Rd
label is a PC#relative expression. See Section 3.3.6 (p. 42) .
ADR determines the address by adding an immediate value to the PC, and writes the result to the
destination register.
ADR produces position#independent code, because the address is PC#relative.
If you use ADR to generate a target address for a BX or BLX instruction, you must ensure that bit[0] of
the address you generate is set to1 for correct execution.
Values of label must be within the range of #4095 to +4095 from the address in the PC.
Note
Rd must not be SP and must not be PC.
This instruction does not change the flags.
Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset.
op{type}{cond} Rt, [Rn {, #offset}]
Mnemonic
STR{type}
STR{type}T
STREX{type} Store Register Exclusive
ADR
is an optional condition code, see Section 3.3.7 (p. 43) .
is the destination register.
You might have to use the .W suffix to get the maximum offset range or to generate
addresses that are not word-aligned. See Section 3.3.8 (p. 45) .
Brief description
Store Register using register offset
Store Register with unprivileged access
R1, TextMessage
; Write address value of a location labelled as
; TextMessage to R1
See
Section 3.4.3 (p. 48)
Section 3.4.4 (p. 50)
Section 3.4.8 (p. 54)
...the world's most energy friendly microcontrollers
; immediate offset
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