EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 40

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.3.4.1 ASR
3.3.4.2 LSR
2011-02-04 - d0002_Rev1.00
• directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the result is written to a destination
• during the calculation of Operand2 by the instructions that specify the second operand as a register
The permitted shift lengths depend on the shift type and the instruction, see the individual instruction
description or Section 3.3.3 (p. 38) . If the shift length is 0, no shift occurs. Register shift operations
update the carry flag except when the specified shift length is 0. The following sub-sections describe
the various shift operations and how they affect the carry flag. In these descriptions, Rm is the register
containing the value to be shifted, and n is the shift length.
Arithmetic shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places,
into the right-hand 32-n bits of the result. And it copies the original bit[31] of the register into the left#hand
n bits of the result. See Figure 3.1 (p. 40) .
You can use the ASR #n operation to divide the value in the register Rm by 2
rounded towards negative-infinity.
When the instruction is ASRS or when ASR #n is used in Operand2 with the instructions MOVS, MVNS,
ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1],
of the register Rm.
Note
Figure 3.1. ASR #3
Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into
the right-hand 32-n bits of the result. And it sets the left#hand n bits of the result to 0. See Figure 3.2 (p.
41) .
You can use the LSR #n operation to divide the value in the register Rm by 2
as an unsigned integer.
When the instruction is LSRS or when LSR #n is used in Operand2 with the instructions MOVS, MVNS,
ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1],
of the register Rm.
Note
register
with shift, see Section 3.3.3 (p. 38) . The result is used by the instruction.
31
• If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.
• If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm.
• If n is 32 or more, then all the bits in the result are cleared to 0.
• If n is 33 or more and the carry flag is updated, it is updated to 0.
...
...the world's most energy friendly microcontrollers
40
5
4
3
n
www.energymicro.com
, if the value is regarded
2
n
, with the result being
1 0
Carry
Flag