EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 88

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4 The Cortex-M3 Peripherals
4.1 About the peripherals
4.2 Nested Vectored Interrupt Controller
2011-02-04 - d0002_Rev1.00
The address map of the Private peripheral bus (PPB) is:
Table 4.1. Core peripheral register regions
1
will read as zero if MPU is not present.
In register descriptions:
• the register type is described as follows:
• the required privilege gives the privilege level required to access the register, as follows:
This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The
NVIC supports:
• The number of interrupts given by Table 1.1 (p. 5) .
• A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower priority,
• Level detection of interrupt signals.
• Dynamic reprioritization of interrupts.
• Grouping of priority values into group priority and subpriority fields.
• Interrupt tail-chaining.
The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead. This provides low latency exception handling. The hardware
implementation of the NVIC registers is:
Table 4.2. NVIC register summary
Software can read the MPU Type Register at 0xE000ED90 to test for the presence of a memory protection unit (MPU). Register
Address
0xE000E008-0xE000E00F
0xE000E010-0xE000E01F
0xE000E100-0xE000E4EF
0xE000ED00-0xE000ED3F
0xE000ED90-0xE000EDB8
0xE000EF00-0xE000EF03
Address
0xE000E100-
0xE000E104
0XE000E180-
0XE000E184
RW Read and write.
RO Read-only.
WO Write-only.
Privileged
Unprivileged
so level 0 is the highest interrupt priority.
Name
ISER0-
ISER1
ICER0-
ICER1
Only privileged software can access the register.
Both unprivileged and privileged software can access the register.
Core peripheral
System control block
System timer
Nested Vectored Interrupt Controller
System control block
Memory protection unit
Nested Vectored Interrupt Controller
Type
RW
RW
Required
privilege
Privileged
Privileged
Reset value Description
0x00000000 Section 4.2.2 (p. 89)
0x00000000 Section 4.2.3 (p. 90)
...the world's most energy friendly microcontrollers
88
Description
Table 4.12 (p. 94)
Table 4.32 (p. 111)
Table 4.2 (p. 88)
Table 4.12 (p. 94)
Section 4.5.1 (p. 114)
Table 4.2 (p. 88)
1
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