EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 47

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.4.2.2 Operation
2011-02-04 - d0002_Rev1.00
op{type}{cond} Rt, [Rn, #offset]!
op{type}{cond} Rt, [Rn], #offset
opD{cond} Rt, Rt2, [Rn {, #offset}]
opD{cond} Rt, Rt2, [Rn, #offset]!
opD{cond} Rt, Rt2, [Rn], #offset
where:
op
type
cond
Rt
Rn
offset is an offset from Rn. If offset is omitted, the address is the contents of Rn.
Rt2
LDR instructions load one or two registers with a value from memory.
STR instructions store one or two register values to memory.
Load and store instructions with immediate offset can use the following addressing modes:
Offset addressing
Pre-indexed addressing
Post-indexed addressing
is one of:
LDR Load Register.
STR Store Register.
is one of:
B
SB signed byte, sign extend to 32 bits (LDR only).
H
SH signed halfword, sign extend to 32 bits (LDR only).
#
is an optional condition code, see Section 3.3.7 (p. 43) .
is the register to load or store.
is the register on which the memory address is based.
is the additional register to load or store for two-word operations.
unsigned byte, zero extend to 32 bits on loads.
unsigned halfword, zero extend to 32 bits on loads.
omit, for word.
The offset value is added to or subtracted from the address obtained
from the register Rn. The result is used as the address for the memory
access. The register Rn is unaltered. The assembly language syntax
for this mode is:
[Rn, #offset]
The offset value is added to or subtracted from the address obtained
from the register Rn. The result is used as the address for the memory
access and written back into the register Rn. The assembly language
syntax for this mode is:
[Rn, #offset]!
The address obtained from the register Rn is used as the address
for the memory access. The offset value is added to or subtracted
from the address, and written back into the register Rn. The assembly
language syntax for this mode is:
[Rn], #offset
...the world's most energy friendly microcontrollers
; pre-indexed
; post-indexed
; immediate offset, two words
; pre-indexed, two words
; post-indexed, two words
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