EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 82

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.10.3.4 Examples
3.10.4 DSB
3.10.4.1 Syntax
3.10.4.2 Operation
3.10.4.3 Condition flags
3.10.4.4 Examples
3.10.5 ISB
3.10.5.1 Syntax
3.10.5.2 Operation
3.10.5.3 Condition flags
3.10.5.4 Examples
2011-02-04 - d0002_Rev1.00
Data Synchronization Barrier.
DSB{cond}
where:
cond is an optional condition code, see Section 3.3.7 (p. 43) .
DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in
program order, do not execute until the DSB instruction completes. The DSB instruction completes when
all explicit memory accesses before it complete.
This instruction does not change the flags.
Instruction Synchronization Barrier.
ISB{cond}
where:
cond is an optional condition code, see Section 3.3.7 (p. 43) .
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all
instructions following the ISB are fetched from cache or memory again, after the ISB instruction has
been completed.
This instruction does not change the flags.
DMB
DSB ; Data Synchronisation Barrier
; Data Memory Barrier
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