EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 58

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.5.1.3 Restrictions
3.5.1.4 Condition flags
3.5.1.5 Examples
2011-02-04 - d0002_Rev1.00
The SBC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is clear, the
result is reduced by one.
The RSB instruction subtracts the value in Rn from the value of Operand2. This is useful because of
the wide range of options for Operand2.
Use ADC and SBC to synthesize multiword arithmetic, see Section 3.5.1.6 (p. 59) .
See also Section 3.4.1 (p. 46) .
Note
In these instructions:
• Operand2 must not be SP and must not be PC
• Rd can be SP only in ADD and SUB, and only with the additional restrictions:
• Rn can be SP only in ADD and SUB
• Rd can be PC only in the ADD{cond} PC, PC, Rm instruction where:
• with the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and SUB,
When Rd is PC in the ADD{cond} PC, PC, Rm instruction:
• bit[0] of the value written to the PC is ignored
• a branch occurs to the address created by forcing bit[0] of that value to 0.
If S is specified, these instructions update the N, Z, C and V flags according to the result.
• Rn must also be SP
• any shift in Operand2 must be limited to a maximum of 3 bits using LSL
• you must not specify the S suffix
• Rm must not be PC and must not be SP
• if the instruction is conditional, it must be the last instruction in the IT block
and only with the additional restrictions:
• you must not specify the S suffix
• the second operand must be a constant in the range 0 to 4095.
Note
ADD
SUBS
RSB
ADCHI
ADDW is equivalent to the ADD syntax that uses the imm12 operand. SUBW is equivalent to
the SUB syntax that uses the imm12 operand.
• When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded
• If you want to generate the address of an instruction, you have to adjust the constant
R2, R1, R3
R8, R6, #240
R4, R4, #1280
R11, R0, R3
to b00 before performing the calculation, making the base address for the calculation
word-aligned.
based on the value of the PC. ARM recommends that you use the ADR instruction
instead of ADD or SUB with Rn equal to the PC, because your assembler automatically
calculates the correct constant for the ADR instruction.
; Sets the flags on the result
; Subtracts contents of R4 from 1280
; Only executed if C flag set and Z
; flag clear
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