EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 109

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.3.12 Hard Fault Status Register
2011-02-04 - d0002_Rev1.00
Note
The HFSR gives information about events that activate the hard fault handler. See the register summary
in Table 4.12 (p. 94) for its attributes.
This register is read, write to clear. This means that bits in the register read normally, but writing 1 to
any bit clears that bit to 0. The bit assignments are:
Table 4.29. HFSR bit assignments
31 30
Bits
[1]
[0]
Bits
[31]
[30]
[29:2]
[1]
29
Name
DEBUGEVT
FORCED
-
VECTTBL
FORCED
DEBUGEVT
Name
INVSTATE
UNDEFINSTR
The UFSR bits are sticky. This means as one or more fault occurs, the associated bits are
set to 1. A bit that is set to 1 is cleared to 0 only by writing 1 to that bit, or by a reset.
Function
Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise
behavior is Unpredictable.
Indicates a forced hard fault, generated by escalation of a fault with configurable priority that
cannot be handles, either because of priority or because it is disabled:
0 = no forced hard fault
1 = forced hard fault.
When this bit is set to 1, the hard fault handler must read the other fault status registers to find
the cause of the fault.
Reserved.
Indicates a bus fault on a vector table read during exception processing:
0 = no bus fault on vector table read
1 = bus fault on vector table read.
This error is always handled by the hard fault handler.
Function
When this bit is set to 1, the PC value stacked for the exception return points to the instruction
that tried to perform the illegal load of the PC.
Invalid state usage fault:
0 = no invalid state usage fault
1 = the processor has attempted to execute an instruction that makes illegal use of the EPSR.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction
that attempted the illegal use of the EPSR.
This bit is not set to 1 if an undefined instruction uses the EPSR.
Undefined instruction usage fault:
0 = no undefined instruction usage fault
1 = the processor has attempted to execute an undefined instruction.
When this bit is set to 1, the PC value stacked for the exception return points to the undefined
instruction.
An undefined instruction is an instruction that the processor cannot decode.
Reserved
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Reserved
VECTTBL
2 1 0