EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 41

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.3.4.3 LSL
3.3.4.4 ROR
2011-02-04 - d0002_Rev1.00
Figure 3.2. LSR #3
Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n places, into
the left-hand 32-n bits of the result. And it sets the right#hand n bits of the result to 0. See Figure 3.3 (p.
41) .
You can use he LSL #n operation to multiply the value in the register Rm by 2
as an unsigned integer or a two’s complement signed integer. Overflow can occur without warning.
When the instruction is LSLS or when LSL #n, with non-zero n, is used in Operand2 with the instructions
MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted
out, bit[32-n], of the register Rm. These instructions do not affect the carry flag when used with LSL #0.
Note
Figure 3.3. LSL #3
Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the
right-hand 32-n bits of the result. And it moves the right#hand n bits of the register into the left#hand
n bits of the result. See Figure 3.4 (p. 42) .
When the instruction is RORS or when ROR #n is used in Operand2 with the instructions MOVS, MVNS,
ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit rotation, bit[n-1],
of the register Rm.
Note
Carry
Flag
31
0
0
31
0
• If n is 32 or more, then all the bits in the result are cleared to 0.
• If n is 33 or more and the carry flag is updated, it is updated to 0.
• If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is
• ROR with shift length, n, more than 32 is the same as ROR with shift length n-32.
updated, it is updated to bit[31] of Rm.
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41
5
4
5
n
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3
, if the value is regarded
4
2
3
2
0
1 0
0
1 0
0
Carry
Flag