EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 91

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.2.5 Interrupt Clear-pending Registers
4.2.6 Interrupt Active Bit Registers
2011-02-04 - d0002_Rev1.00
Table 4.6. ISPR bit assignments
Note
The ICPR0 and ICPR1 registers remove the pending state from interrupts, and show which interrupts
are pending. See:
• the register summary in Table 4.2 (p. 88) for the register attributes
• Table 4.3 (p. 89) for which interrupts are controlled by each register.
The bit assignments are:
Table 4.7. ICPR bit assignments
Note
The IABR0 and IABR1 registers indicate which interrupts are active. See:
• the register summary in Table 4.2 (p. 88) for the register attributes
• Table 4.3 (p. 89) for which interrupts are controlled by each register.
The bit assignments are:
31
Bits
[31:0]
Bits
[31:0]
Name
SETPEND
Name
CLRPEND
Writing 1 to the ISPR bit corresponding to:
• an interrupt that is pending has no effect
• a disabled interrupt sets the state of that interrupt to pending.
Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt.
Function
Interrupt set-pending bits.
Write:
0 = no effect
1 = changes interrupt state to
pending.Read:
0 = interrupt is not pending
1 = interrupt is pending.
Function
Interrupt clear-pending bits.
Write:
0 = no effect
1 = removes pending state an
interrupt.Read:
0 = interrupt is not pending
1 = interrupt is pending.
CLRPEND bits
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