EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 16

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.2.2 Memory system ordering of memory accesses
2.2.3 Behavior of memory accesses
2011-02-04 - d0002_Rev1.00
Device
Strongly-ordered
The different ordering requirements for Device and Strongly-ordered memory mean that the memory
system can buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory.
The additional memory attributes include.
Execute Never (XN)
For most memory accesses caused by explicit memory access instructions, the memory system does not
guarantee that the order in which the accesses complete matches the program order of the instructions,
providing this does not affect the behavior of the instruction sequence. Normally, if correct program
execution depends on two memory accesses completing in program order, software must insert a
memory barrier instruction between the memory access instructions, see Section 2.2.4 (p. 17) .
However, the memory system does guarantee some ordering of accesses to Device and Strongly-
ordered memory. For two memory access instructions A1 and A2, if A1 occurs before A2 in program
order, the ordering of the memory accesses caused by two instructions is:
Where:
-
< Means that accesses are observed in program order, that is, A1 is always observed before A2.
The behavior of accesses to each region in the memory map is:
Table 2.11. Memory access behavior
Address
range
0x00000000-
0x1FFFFFFF
0x20000000-
0x3FFFFFFF
0x40000000-
0x5FFFFFFF
A1
Means that the memory system does not guarantee the ordering of the accesses.
Device access, non-shareable
Device access, shareable
Strongly-ordered access
Memory region
Code
SRAM
Peripheral
Norm al access
The processor preserves transaction order relative to other transactions to
Device or Strongly-ordered memory.
The processor preserves transaction order relative to all other transactions.
Memory
type
Normal
Normal
Device
Means the processor prevents instruction accesses. Any attempt to fetch an
instruction from an XN region causes a memory management fault exception.
A2
1
1
1
XN
-
-
XN
Norm al
access
1
-
-
-
-
Description
Executable region for program code. You can also put data here.
Executable region for data. You can also put code here.This region
includes bit band and bit band alias areas, see Table 2.12 (p. 18)
.
This region includes bit band and bit band alias areas, see
Table 2.13 (p. 18) .
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16
Non-shareable
<
<
-
-
Device access
Shareable
<
<
-
-
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Strongly-
ordered
access
<
<
<
-