EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 51

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.4.5 LDR, PC#relative
3.4.5.1 Syntax
3.4.5.2 Operation
3.4.5.3 Restrictions
2011-02-04 - d0002_Rev1.00
Load register from memory.
LDR{type}{cond} Rt, label
LDRD{cond} Rt, Rt2, label
where:
type
cond
Rt
Rt2
label is a PC#relative expression. See Section 3.3.6 (p. 42) .
LDR loads a register with a value from a PC-relative memory address. The memory address is specified
by a label or by an offset from the PC.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords
can either be signed or unsigned. See Section 3.3.5 (p. 42) .
label must be within a limited range of the current instruction. Table 3.7 (p. 51) shows the possible
offsets between label and the PC.
Table 3.7. Offset ranges
Note
In these instructions:
• Rt can be SP or PC only for word loads
• Rt2 must not be SP and must not be PC
• Rt must be different from Rt2.
When Rt is PC in a word load instruction:
• bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned
Instruction type
Word, halfword, signed halfword, byte, signed byte
Two words
address
is one of:
B
SB signed byte, sign extend to 32 bits.
H
SH signed halfword, sign extend to 32 bits.
#
is an optional condition code, see Section 3.3.7 (p. 43) .
is the register to load or store.
is the second register to load or store.
You might have to use the .W suffix to get the maximum offset range. See Section 3.3.8 (p.
45) .
unsigned byte, zero extend to 32 bits.
unsigned halfword, zero extend to 32 bits.
omit, for word.
; Load two words
Offset range
#4095 to 4095
#1020 to 1020
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