EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 50

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.4.4 LDR and STR, unprivileged
3.4.4.1 Syntax
3.4.4.2 Operation
3.4.4.3 Restrictions
3.4.4.4 Condition flags
3.4.4.5 Examples
2011-02-04 - d0002_Rev1.00
Load and Store with unprivileged access.
op{type}T{cond} Rt, [Rn {, #offset}]
where:
op
type
cond
Rt
Rn
offset is an offset from Rn and can be 0 to 255. If offset is omitted, the address is the value in Rn.
These load and store instructions perform the same function as the memory access instructions with
immediate offset, see Section 3.4.2 (p. 46) . The difference is that these instructions have only
unprivileged access even when used in privileged software.
When used in unprivileged software, these instructions behave in exactly the same way as normal
memory access instructions with immediate offset.
In these instructions:
• Rn must not be PC
• Rt must not be SP and must not be PC.
These instructions do not change the flags.
LDRSB
STR
STRBTEQ
LDRHT
is one of:
LDR Load Register.
STR Store Register.
is one of:
B
SB signed byte, sign extend to 32 bits (LDR only).
H
SH signed halfword, sign extend to 32 bits (LDR only).
#
is an optional condition code, see Section 3.3.7 (p. 43) .
is the register to load or store.
is the register on which the memory address is based.
R0, [R5, R1, LSL #1] ; Read byte value from an address equal to
R0, [R1, R2, LSL #2] ; Stores R0 to an address equal to sum of R1
R4, [R7]
R2, [R2, #8]
unsigned byte, zero extend to 32 bits on loads.
unsigned halfword, zero extend to 32 bits on loads.
omit, for word.
; Conditionally store least significant byte in
; R4 to an address in R7, with unprivileged access
; Load halfword value from an address equal to
; sum of R2 and 8 into R2, with unprivileged access
; sum of R5 and two times R1, sign extended it
; to a word value and put it in R0
; and four times R2
; immediate offset
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