EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 102

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.3.9 System Handler Priority Registers
2011-02-04 - d0002_Rev1.00
The SHPR1-SHPR3 registers set the priority level, 0 to 7 of the exception handlers that have configurable
priority.
SHPR1-SHPR3 are byte accessible. See the register summary in Table 4.12 (p. 94) for their
attributes.
The system fault handlers and the priority field and register for each handler are:
Table 4.21. System fault handler priority fields
Bits
[8]
[7:5]
[4]
[3]
[2]
[1]
[0]
Handler
Memory management fault
Bus fault
Usage fault
SVCall
PendSV
Name
BFHFNMIGN
-
DIV_0_TRP
UNALIGN_TRP
-
USERSETMPEND
NONEBASETHRDENA
Field
PRI_4
PRI_5
PRI_6
PRI_11
PRI_14
Function
On exception entry, the processor uses bit[9] of the stacked PSR to indicate the
stack alignment. On return from the exception it uses this stacked bit to restore the
correct stack alignment.
Enables handlers with priority -1 or -2 to ignore data bus faults caused by load and
store instructions. This applies to the hard fault, NMI, and FAULTMASK escalated
handlers:
0 = data bus faults caused by load and store instructions cause a lock-up
1 = handlers running at priority -1 and -2 ignore data bus faults caused by load and
store instructions.
Set this bit to 1 only when the handler and its data are in absolutely safe memory.
The normal use of this bit is to probe system devices and bridges to detect control
path problems and fix them.
Reserved.
Enables faulting or halting when the processor executes an SDIV or UDIV
instruction with a divisor of 0:
0 = do not trap divide by 0
1 = trap divide by 0.
When this bit is set to 0,a divide by zero returns a quotient of 0.
Enables unaligned access traps:
0 = do not trap unaligned halfword and word accesses1 = trap unaligned halfword
and word accesses.
If this bit is set to 1, an unaligned access generates a usage fault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of
whether UNALIGN_TRP is set to 1.
Reserved.
Enables unprivileged software access to the STIR, see Section 4.2.8 (p. 93) :
0 = disable1 = enable.
Indicates how the processor enters Thread mode:
0 = processor can enter Thread mode only when no exception is active.
1 = processor can enter Thread mode from any level under the control of an
EXC_RETURN value, see Section 2.3.7.2 (p. 27) .
Register description
Section 4.3.9.1 (p. 103)
Section 4.3.9.2 (p. 103)
Section 4.3.9.2 (p. 103)
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