EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 49

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.4.3.1 Syntax
3.4.3.2 Operation
3.4.3.3 Restrictions
3.4.3.4 Condition flags
3.4.3.5 Examples
2011-02-04 - d0002_Rev1.00
op{type}{cond} Rt, [Rn, Rm {, LSL #n}]
where:
op
type
cond
Rt
Rn
Rm
LSL #n is an optional shift, with n in the range 0 to 3.
LDR instructions load a register with a value from memory.
STR instructions store a register value into memory.
The memory address to load from or store to is at an offset from the register Rn. The offset is specified
by the register Rm and can be shifted left by up to 3 bits using LSL.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords
can either be signed or unsigned. See Section 3.3.5 (p. 42) .
In these instructions:
• Rn must not be PC
• Rm must not be SP and must not be PC
• Rt can be SP only for word loads and word stores
• Rt can be PC only for word loads.
When Rt is PC in a word load instruction:
• bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned
• if the instruction is conditional, it must be the last instruction in the IT block.
These instructions do not change the flags.
address
STR
is one of:
LDR Load Register.
STR Store Register.
is one of:
B
SB signed byte, sign extend to 32 bits (LDR only).
H
SH signed halfword, sign extend to 32 bits (LDR only).
#
is an optional condition code, see Section 3.3.7 (p. 43) .
is the register to load or store.
is the register on which the memory address is based.
is a register containing a value to be used as the offset.
R0, [R5, R1]
unsigned byte, zero extend to 32 bits on loads.
unsigned halfword, zero extend to 32 bits on loads.
omit, for word.
; Store value of R0 into an address equal to
; sum of R5 and R1
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