EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 53

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.4.6.3 Restrictions
3.4.6.4 Condition flags
3.4.6.5 Examples
3.4.6.6 Incorrect examples
3.4.7 PUSH and POP
3.4.7.1 Syntax
2011-02-04 - d0002_Rev1.00
the lowest memory address and the highest number register using the highest memory address. If the
writeback suffix is specified, the value of Rn + 4 * (n-1) is written back to Rn.
For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at 4-byte
intervals ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in reglist. The accesses
happen in order of decreasing register numbers, with the highest numbered register using the highest
memory address and the lowest number register using the lowest memory address. If the writeback
suffix is specified, the value of Rn - 4 * (n-1) is written back to Rn.
The PUSH and POP instructions can be expressed in this form. See Section 3.4.7 (p. 53) for details.
In these instructions:
• Rn must not be PC
• reglist must not contain SP
• in any STM instruction, reglist must not contain PC
• in any LDM instruction, reglist must not contain PC if it contains LR
• reglist must not contain Rn if you specify the writeback suffix.
When PC is in reglist in an LDM instruction:
• bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this
• if the instruction is conditional, it must be the last instruction in the IT block.
These instructions do not change the flags.
Push registers onto, and pop registers off a full-descending stack.
PUSH{cond} reglist
POP{cond} reglist
where:
cond
reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges. It must be
halfword-aligned address
LDM
STMDB
STM
LDM
is an optional condition code, see Section 3.3.7 (p. 43) .
comma separated if it contains more than one register or register range.
R8,{R0,R2,R9}
R1!,{R3#R6,R11,R12}
R5!,{R5,R4,R9} ; Value stored for R5 is unpredictable
R2, {}
; There must be at least one register in the list
; LDMIA is a synonym for LDM
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