EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 94

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.2.10 NVIC design hints and tips
4.2.10.1 NVIC programming hints
4.3 System control block
2011-02-04 - d0002_Rev1.00
Ensure software uses correctly aligned register accesses. The processor does not support unaligned
accesses to NVIC registers. See the individual register descriptions for the supported access sizes.
A interrupt can enter pending state even it is disabled.
Before programming VTOR to relocate the vector table, ensure the vector table entries of the new vector
table are setup for fault handlers, NMI and all enabled exception like interrupts. For more information
see Section 4.3.5 (p. 98) .
Software uses the CPSIE I and CPSID I instructions to enable and disable interrupts. The CMSIS
provides the following intrinsic functions for these instructions:
void __disable_irq(void)
void __enable_irq(void)
In addition, the CMSIS provides a number of functions for NVIC control, including:
Table 4.11. CMSIS functions for NVIC control
For more information about these functions see the CMSIS documentation.
The System control block (SCB) provides system implementation information, and system control.
This includes configuration, control, and reporting of the system exceptions. The system control block
registers are:
Table 4.12. Summary of the system control block registers
CMSIS interrupt control function
void NVIC_SetPriorityGrouping(uint32_t
priority_grouping)
void NVIC_EnableIRQ(IRQn_t IRQn)
void NVIC_DisableIRQ(IRQn_t IRQn)
uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn)
void NVIC_SetPendingIRQ (IRQn_t IRQn)
void NVIC_ClearPendingIRQ (IRQn_t IRQn)
uint32_t NVIC_GetActive (IRQn_t IRQn)
void NVIC_SetPriority (IRQn_t IRQn, uint32_t
priority)
uint32_t NVIC_GetPriority (IRQn_t IRQn)
void NVIC_SystemReset (void)
Address
0xE000E008 ACTLR
If the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state
of the interrupt changes to inactive.
Name
Type
RW
Required
privilege
Privileged
// Enable Interrupts
// Disable Interrupts
Reset value Description
0x00000000 Section 4.3.2 (p. 95)
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Description
Set the priority grouping
Enable IRQn
Disable IRQn
Return true (IRQ-Number) if IRQn is pending
Set IRQn pending
Clear IRQn pending status
Return the IRQ number of the active interrupt
Set priority for IRQn
Read priority of IRQn
Reset the system
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