EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 33

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3 The Cortex-M3 Instruction Set
3.1 Instruction set summary
2011-02-04 - d0002_Rev1.00
The processor implements a version of the Thumb instruction set. Table 3.1 (p. 33) lists the supported
instructions.
Note
Table 3.1. Cortex-M3 instructions
Mnemonic
ADC, ADCS
ADD, ADDS
ADD, ADDW
ADR
AND, ANDS
ASR, ASRS
B
BFC
BFI
BIC, BICS
BKPT
BL
BLX
BX
CBNZ
CBZ
In Table 3.1 (p. 33) :
• angle brackets, <>, enclose alternative forms of the operand
• braces, {}, enclose optional operands
• the Operands column is not exhaustive
• Op2 is a flexible second operand that can be either a register or a constant
• most instructions can use an optional condition code suffix.
For more information on the instructions and operands, see the instruction descriptions.
Operands
{Rd,} Rn, Op2
{Rd,} Rn, Op2
{Rd,} Rn, #imm12
Rd, label
{Rd,} Rn, Op2
Rd, Rm, <Rs|#n>
label
Rd, #lsb, #width
Rd, Rn, #lsb,
#width
{Rd,} Rn, Op2
#imm
label
Rm
Rm
Rn, label
Rn, label
Brief description
Add with Carry
Add
Add
Load PC-relative address
Logical AND
Arithmetic Shift Right
Branch
Bit Field Clear
Bit Field Insert
Bit Clear
Breakpoint
Branch with Link
Branch indirect with Link
Branch indirect
Compare and Branch if Non Zero
Compare and Branch if Zero
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33
Flags
N,Z,C,V
N,Z,C,V
N,Z,C,V
-
N,Z,C
N,Z,C
-
-
-
N,Z,C
-
-
-
-
-
-
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Page
Section 3.5.1 (p.
57)
Section 3.5.1 (p.
57)
Section 3.5.1 (p.
57)
Section 3.4.1 (p.
46)
Section 3.5.2 (p.
59)
Section 3.5.3 (p.
60)
Section 3.9.1 (p.
74)
Section 3.8.1 (p.
71)
Section 3.8.1 (p.
71)
Section 3.5.2 (p.
59)
Section 3.10.1 (p.
80)
Section 3.9.1 (p.
74)
Section 3.9.1 (p.
74)
Section 3.9.1 (p.
74)
Section 3.9.2 (p.
75)
Section 3.9.2 (p.
75)