EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 127

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Should Be Zero (SBZ)
Should
Preserved (SBZP)
Thread-safe
Thumb instruction
Unaligned
Undefined
Unpredictable (UNP)
Warm reset
WA
WB
Word
Write
Write-allocate (WA)
Write-back (WB)
Write buffer
Write-through (WT)
2011-02-04 - d0002_Rev1.00
Be
Zero
or
Write as 0, or all 0s for bit fields, by software. Writing as 1 produces
Unpredictable results.
Write as 0, or all 0s for bit fields, by software, or preserved by writing the
same value back that has been previously read from the same field on the
same processor.
In a multi-tasking environment, thread-safe functions use safeguard
mechanisms when accessing shared resources, to ensure correct operation
without the risk of shared access conflicts.
One or two halfwords that specify an operation for a processor to perform.
Thumb instructions must be halfword-aligned.
A data item stored at an address that is not divisible by the number of bytes
that defines the data size is said to be unaligned. For example, a word stored
at an address that is not divisible by four.
Indicates an instruction that generates an Undefined instruction exception.
You cannot rely on the behavior. Unpredictable behavior must not represent
security holes. Unpredictable behavior must not halt or hang the processor,
or any parts of the system.
Also known as a core reset. Initializes the majority of the processor excluding
the debug controller and debug logic. This type of reset is useful if you are
using the debugging features of a processor.
See Write-allocate.
See Write-back.
A 32-bit data item.
Writes are defined as operations that have the semantics of a store. Writes
include the Thumb instructions STM, STR, STRH, STRB, and PUSH.
In a write-allocate cache, a cache miss on storing data causes a cache line
to be allocated into the cache.
In a write-back cache, data is only written to main memory when it is forced
out of the cache on line replacement following a cache miss. Otherwise,
writes by the processor only update the cache. This is also known as
copyback.
A block of high-speed memory, arranged as a FIFO buffer, between the
data cache and main memory, whose purpose is to optimize stores to main
memory.
In a write-through cache, data is written to main memory at the same time
as the cache is updated.
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