EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 42

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.3.4.5 RRX
3.3.5 Address alignment
3.3.6 PC#relative expressions
2011-02-04 - d0002_Rev1.00
Figure 3.4. ROR #3
Rotate right with extend moves the bits of the register Rm to the right by one bit. And it copies the carry
flag into bit[31] of the result. See Figure 3.5 (p. 42) .
When the instruction is RRXS or when RRX is used in Operand2 with the instructions MOVS, MVNS, ANDS,
ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[0] of the register Rm.
Figure 3.5. RRX
An aligned access is an operation where a word-aligned address is used for a word, dual word, or
multiple word access, or where a halfword-aligned address is used for a halfword access. Byte accesses
are always aligned.
The Cortex-M3 processor supports unaligned access only for the following instructions:
• LDR, LDRT
• LDRH, LDRHT
• LDRSH, LDRSHT
• STR, STRT
• STRH, STRHT
All other load and store instructions generate a usage fault exception if they perform an unaligned access,
and therefore their accesses must be address aligned. For more information about usage faults see
Section 2.4 (p. 28) .
Unaligned accesses are usually slower than aligned accesses. In addition, some memory regions might
not support unaligned accesses. Therefore, ARM recommends that programmers ensure that accesses
are aligned. To avoid accidental generation of unaligned accesses, use the UNALIGN_TRP bit in the
Configuration and Control Register to trap all unaligned accesses, see Section 4.3.8 (p. 101) .
A PC#relative expression or label is a symbol that represents the address of an instruction or literal
data. It is represented in the instruction as the PC value plus or minus a numeric offset. The assembler
calculates the required offset from the label and the address of the current instruction. If the offset is too
big, the assembler produces an error.
31
31 30
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2
1 0
1 0
Carry
Carry
Flag
Flag