EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 14

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.2 Memory model
2011-02-04 - d0002_Rev1.00
• the names of:
• a device-independent interface for RTOS kernels, including a debug channel.
The CMSIS includes address definitions and data structures for the core peripherals in the Cortex-M3
processor. It also includes optional interfaces for middleware components comprising a TCP/IP stack
and a Flash file system.
CMSIS simplifies software development by enabling the reuse of template code and the combination
of CMSIS-compliant software components from various middleware vendors. Software vendors can
expand the CMSIS to include their peripheral definitions and access functions for those peripherals.
This document includes the register names defined by the CMSIS, and gives short descriptions of the
CMSIS functions that address the processor core and the core peripherals.
Note
The following sections give more information about the CMSIS:
• Section 2.5.4 (p. 32)
• Section 3.2 (p. 37)
• Section 4.2.1 (p. 89)
• Section 4.2.10.1 (p. 94) .
This section describes the processor memory map, the behavior of memory accesses, and the bit-
banding features. The processor has a fixed memory map that provides up to 4GB of addressable
memory. The memory map is:
• access peripheral registers
• define exception vectors
• the registers of the core peripherals
• the core exception vectors
This document uses the register short names defined by the CMSIS. In a few cases these
differ from the architectural short names that might be used in other documents.
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