EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 27

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.3.7.1 Exception entry
2.3.7.2 Exception return
2011-02-04 - d0002_Rev1.00
Exception entry occurs when there is a pending exception with sufficient priority and either:
• the processor is in Thread mode
• the new exception is of higher priority than the exception being handled, in which case the new
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask registers, see
Section 2.1.3.6 (p. 11) . An exception with less priority than this is pending but is not handled by
the processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving
exception, the processor pushes information onto the current stack. This operation is referred as stacking
and the structure of eight data words is referred as stack frame. The stack frame contains the following
information:
• R0-R3, R12
• Return address
• PSR
• LR.
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. Unless
stack alignment is disabled, the stack frame is aligned to a double-word address. If the STKALIGN bit of
the Configuration Control Register (CCR) is set to 1, stack align adjustment is performed during stacking.
The stack frame includes the return address. This is the address of the next instruction in the interrupted
program. This value is restored to the PC at exception return so that the interrupted program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the exception
handler start address from the vector table. When stacking is complete, the processor starts executing
the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR.
This indicates which stack pointer corresponds to the stack frame and what operation mode the was
processor was in before the entry occurred.
If no higher priority exception occurs during exception entry, the processor starts executing the exception
handler and automatically changes the status of the corresponding pending interrupt to active.
If another higher priority exception occurs during exception entry, the processor starts executing the
exception handler for this exception and does not change the pending status of the earlier exception.
This is the late arrival case.
Exception return occurs when the processor is in Handler mode and executes one of the following
instructions to load the EXC_RETURN value into the PC:
• a POP instruction that includes the PC
• a BX instruction with any register.
• an LDR or LDM instruction with the PC as the destination.
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on
this value to detect when the processor has completed an exception handler. The lowest four bits of
exception preempts the original exception.
exception enters the execute stage of the processor. On return from the exception
handler of the late-arriving exception, the normal tail-chaining rules apply.
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