EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 55

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.4.8.2 Operation
3.4.8.3 Restrictions
3.4.8.4 Condition flags
3.4.8.5 Examples
2011-02-04 - d0002_Rev1.00
STREXH{cond} Rd, Rt, [Rn]
where:
cond
Rd
Rt
Rn
offset is an optional offset applied to the value in Rn. If offset is omitted, the address is the value
LDREX, LDREXB, and LDREXH load a word, byte, and halfword respectively from a memory address.
STREX, STREXB, and STREXH attempt to store a word, byte, and halfword respectively to a memory
address. The address used in any Store-Exclusive instruction must be the same as the address in the
most recently executed Load-exclusive instruction. The value stored by the Store-Exclusive instruction
must also have the same data size as the value loaded by the preceding Load-exclusive instruction.
This means software must always use a Load-exclusive instruction and a matching Store-Exclusive
instruction to perform a synchronization operation, see Section 2.2.7 (p. 20)
If an Store-Exclusive instruction performs the store, it writes 0 to its destination register. If it does not
perform the store, it writes 1 to its destination register. If the Store-Exclusive instruction writes 0 to the
destination register, it is guaranteed that no other process in the system has accessed the memory
location between the Load-exclusive and Store-Exclusive instructions.
For reasons of performance, keep the number of instructions between corresponding Load-Exclusive
and Store-Exclusive instruction to a minimum.
Note
In these instructions:
• do not use PC
• do not use SP for Rd and Rt
• for STREX, Rd must be different from both Rt and Rn
• the value of offset must be a multiple of four in the range 0-1020.
These instructions do not change the flags.
try
MOV
LDREX
CMP
ITT
STREXEQ R0, R1, [LockAddr]
CMPEQ
BNE
....
is an optional condition code, see Section 3.3.7 (p. 43) .
is the destination register for the returned status.
is the register to load or store.
is the register on which the memory address is based.
in Rn.
The result of executing a Store-Exclusive instruction to an address that is different from that
used in the preceding Load-Exclusive instruction is unpredictable.
R1, #0x1
R0, [LockAddr]
R0, #0
EQ
R0, #0
try
; Initialize the ‘lock taken’ value
; Load the lock value
; Is the lock free?
; IT instruction for STREXEQ and CMPEQ
; Try and claim the lock
; Did this succeed?
; No – try again
; Yes – we have the lock
...the world's most energy friendly microcontrollers
55
www.energymicro.com