EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 57

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.5.1 ADD, ADC, SUB, SBC, and RSB
3.5.1.1 Syntax
3.5.1.2 Operation
2011-02-04 - d0002_Rev1.00
Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.
op{S}{cond} {Rd,} Rn, Operand2
op{cond} {Rd,} Rn, #imm12
where:
op
S
cond
Rd
Rn
Operand2 is a flexible second operand. See Section 3.3.3 (p. 38) for details of the options.
imm12
The ADD instruction adds the value of Operand2 or imm12 to the value in Rn.
The ADC instruction adds the values in Rn and Operand2, together with the carry flag.
The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn.
Mnemonic
MVN
ORN
ORR
RBIT
REV
REV16
REVSH
ROR
RRX
RSB
SBC
SUB
SUBW
TEQ
TST
Brief description
Move NOT
Logical OR NOT
Logical OR
Reverse Bits
Reverse byte order in a word
Reverse byte order in each halfword
Reverse byte order in bottom halfword and sign extend
Rotate Right
Rotate Right with Extend
Reverse Subtract
Subtract with Carry
Subtract
Subtract
Test Equivalence
Test
is one of:
ADD Add.
ADC Add with Carry.
SUB Subtract.
SBC Subtract with Carry.
RSB Reverse Subtract.
is an optional suffix. If S is specified, the condition code flags are updated on the result of
the operation, see Section 3.3.7 (p. 43) .
is an optional condition code, see Section 3.3.7 (p. 43) .
is the destination register. If Rd is omitted, the destination register is Rn.
is the register holding the first operand.
is any value in the range 0-4095.
; ADD and SUB only
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57
See
Section 3.5.6 (p. 62)
Section 3.5.2 (p. 59)
Section 3.5.2 (p. 59)
Section 3.5.8 (p. 64)
Section 3.5.8 (p. 64)
Section 3.5.8 (p. 64)
Section 3.5.8 (p. 64)
Section 3.5.3 (p. 60)
Section 3.5.3 (p. 60)
Section 3.5.1 (p. 57)
Section 3.5.1 (p. 57)
Section 3.5.1 (p. 57)
Section 3.5.1 (p. 57)
Section 3.5.9 (p. 65)
Section 3.5.9 (p. 65)
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