EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 31

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.5.1.3 Sleep-on-exit
2.5.2 Wakeup from sleep mode
2.5.2.1 Wakeup from WFI or sleep-on-exit
2.5.2.2 Wakeup from WFE
2.5.3 The Wakeup Interrupt Controller
2011-02-04 - d0002_Rev1.00
• if the register is 0 the processor stops executing instructions and enters sleep mode
• if the register is 1 the processor clears the register to 0 and continues executing instructions without
See Section 3.10.11 (p. 86) for more information.
If the event register is 1, this indicate that the processor must not enter sleep mode on execution
of a WFE instruction. Typically, this is because the processor has executed an SEV instruction, see
Section 3.10.9 (p. 85) . Software cannot access this register directly.
If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the execution of an
exception handler it returns to Thread mode and immediately enters sleep mode. Use this mechanism
in applications that only require the processor to run when an exception occurs.
The conditions for the processor to wakeup depend on the mechanism that cause it to enter sleep mode.
Normally, the processor wakes up only when it detects an exception with sufficient priority to cause
exception entry.
Some embedded systems might have to execute system restore tasks after the processor wakes up, and
before it executes an interrupt handler. To achieve this set the PRIMASK bit to 1 and the FAULTMASK
bit to 0. If an interrupt arrives that is enabled and has a higher priority than current exception priority,
the processor wakes up but does not execute the interrupt handler until the processor sets PRIMASK
to zero. For more information about PRIMASK and FAULTMASK see Section 2.1.3.6 (p. 11) .
The processor wakes up if:
• it detects an exception with sufficient priority to cause exception entry
• in a multiprocessor system, another processor in the system executes an SEV instruction.
In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggers an event and
wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception
entry. For more information about the SCR see Section 4.3.7 (p. 100) .
The Wakeup Interrupt Controller (WIC) is a peripheral that can detect an interrupt and wake the
processor from deep sleep mode. The WIC is enabled only when the DEEPSLEEP bit in the SCR is
set to 1, see Section 4.3.7 (p. 100) .
The WIC is not programmable, and does not have any registers or user interface. It operates entirely
from hardware signals.
When the WIC is enabled and the processor enters deep sleep mode, the power management unit
in the system can power down most of the Cortex-M3 processor. This has the side effect of stopping
the SysTick timer. When the WIC receives an interrupt, it takes a number of clock cycles to wakeup
the processor and restore its state, before it can process the interrupt. This means interrupt latency is
increased in deep sleep mode.
Note
entering sleep mode.
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