EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 38

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.3 About the instruction descriptions
3.3.1 Operands
3.3.2 Restrictions when using PC or SP
3.3.3 Flexible second operand
3.3.3.1 Constant
2011-02-04 - d0002_Rev1.00
This section gives more information about using the instructions.
An instruction operand can be an ARM register, a constant, or another instruction-specific parameter.
Instructions act on the operands and often store the result in a destination register. When there is a
destination register in the instruction, it is usually specified before the operands.
Operands in some instructions are flexible in that they can either be a register or a constant. See
Section 3.3.3 (p. 38) .
Many instructions have restrictions on whether you can use the Program Counter (PC) or Stack Pointer
(SP) for the operands or destination register. See instruction descriptions for more information.
Note
Many general data processing instructions have a flexible second operand. This is shown as Operand2
in the descriptions of the syntax of each instruction.
Operand2 can be a:
• Section 3.3.3.1 (p. 38)
• Section 3.3.3.2 (p. 39)
You specify an Operand2 constant in the form:
Special register
FAULTMASK
BASEPRI
CONTROL
MSP
PSP
Bit[0] of any address you write to the PC with a BX, BLX, LDM, LDR, or POP instruction must
be 1 for correct execution, because this bit indicates the required instruction set, and the
Cortex-M3 processor only supports Thumb instructions.
Access
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
CMSIS function
void __set_PRIMASK (uint32_t
value)
uint32_t __get_FAULTMASK (void)
void __set_FAULTMASK (uint32_t
value)
uint32_t __get_BASEPRI (void)
void __set_BASEPRI (uint32_t
value)
uint32_t __get_CONTROL (void)
void __set_CONTROL (uint32_t
value)
uint32_t __get_MSP (void)
void __set_MSP (uint32_t
TopOfMainStack)
uint32_t __get_PSP (void)
void __set_PSP (uint32_t
TopOfProcStack)
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